Hi folks,
As we prepare ourselves to launch our first blog on hardware modeling using Verilog, we think it is better to give this preamble.
Yes, we use Verilog to model hardware. Actually, we use it to model the behavior of a system. In our 2 decades of experience with colleagues new to Verilog, we see that one of the most misunderstood topics is reg v/s net behavior of Verilog. It is passed-off as a tribal knowledge which says that there are just two thumb rules -
1. If a variable appears on the LHS of an expression in a procedural block, it has to be a reg datatype
2. All other variables can be net datatype
Well, that’s true! But, it has a lot more to it. And a good understanding of this will form a good background in not just model writing
(RTL, behavioral …),but also make you understand more about simulation models as a whole vis-a-vis actual hardware realization.
Besides, please note, a reg datatype does not yield a sequential element, unless specifically used in a particular way suggested to realize a sequential element. Many think that reg variables synthesize into a flip-flop or a latch. Look at the example below -
reg y;
wire a, b;
always @(a or b)
y = a & b;
The above snippet models an AND gate. Where is the sequential element? Note that y is a reg, though!
OK, enough of preamble. In Verilog, there is not just the ‘reg’ keyword that gives a reg datatype. Several other variable types are also of the reg kind.
Let’s see you in the detailed write-up on reg, folks.
Happy reading,
Tech Pubs,
